1. Field of the Invention
The invention in general relates to ferroelectric memory architecture, and more particularly to memory architecture that includes a memory cell with two capacitors and in which the bit lines are driven and the plate line is switched.
2. Statement of the Problem
It is well-known that ferroelectric materials are capable of retaining a polarization which can be used to store information in a non-volatile memory. For example, if a strong enough electric field or voltage is placed across a ferroelectric capacitor, when the voltage is removed, a polarization in the direction of the field remains. If the field is then placed across the same capacitor in the opposite direction, the ferroelectric material switches, and when the field is removed, a polarization in the opposite direction remains. Electronic circuits have been designed to associate the polarization in one direction with a digital logic "1" state, and polarization in the opposite direction with a logic "0" state. See, for example, the circuits described in U.S. Pat. No. 2,876,436 issued on Mar. 3, 1959 to J. R. Anderson. Like other integrated circuit memories, these circuits include memory cells arranged in rows and columns, each memory cell including at least one switch, a capacitor having a pair of plate electrodes, and the memory also including plate lines connected to one plate of the capacitor in each cell, and bit lines connected to the other plate of the capacitor through the switch. In the Anderson patent cited above, the switch is a diode. As known in the art, the switch can be a transistor having a gate, a source and a drain, and the memory includes word lines connected to the control gate of the transistor. The transistor acts as a switch controlled by its gate, to connect the capacitor to the bit line. Information is written into a memory cell by placing either a high or a low voltage on the bit line, turning the transistor on to connect the bit line to the capacitor, and placing a predetermined voltage between the high and low voltage on the plate line. The high voltage causes the memory cell to assume one polarization state, and the low voltage causes the memory cell to assume the opposite polarization state. The memory cell is read by creating a voltage difference between the bit line and plate line, connecting the bit line to the capacitor via the transistor. If the ferroelectric state changes due to the applied voltage, the bit line will assume a first voltage, and if the ferroelectric state does not switch, then the bit line will assume a second voltage. The bit line voltage is compared to a reference voltage that is about half-way between the first and second voltages; if the bit line voltage is below the reference voltage, a sense amp drives an output low, and if the bit line voltage is above the reference voltage, a sense amp drives an output high. In this way, the state of the ferroelectric capacitor prior to reading determines the output state when the cell is read.
In the above-described memory and other similar conventional ferroelectric memories, the plate line is pulsed. The plate line, being relatively long and connected to the electrodes of many capacitors, has a high capacitance. Thus, it takes a relatively long time for the voltage to rise to its full value, with the result that the time to read and write to the memory is long. To speed up the read and write processes, ferroelectric memories in which the plate line is not pulsed have been developed. See U.S. Pat. No. 5,029,128 issued Jul. 2, 1991, to Haruki Toda, and Hiroki Koike et al., "A 60-ns 1-Mb Nonvolatile Ferroelectric Memory With A Nondriven Cell Plate Line Write/Read Scheme, IEEE Journal of Solid State Circuits, Vol. 31, No. 11, November 1996. However, these memories have several other problems summarized below.
Up until recently, all ferroelectric materials tended to fatigue over time, and the switching charge decreased to a point where the cell could no longer be read. Recently, a class of materials, called layered superlattice compounds herein, have been discovered that do not fatigue. However, while the switching charge remains relatively stable in these materials, the materials still age, i.e., the magnitude of the first and second voltages generally depends on the history of the memory cell. For example, depending on the history, both the first and second voltages in one reading on a specific cell will differ by some voltage factor from the first and second voltages of a later reading of the same cell; or the hysteresis curve may drift over times in the order of milliseconds due to redistribution of charge within the capacitor. Thus, while the reference voltage will be between the first and second voltages for one reading, in a later reading both the first and second voltages may be above the reference voltage. This generally results in a misreading of the memory cell. Thus, these memories are not "safe" in that the reading or sensing of the data is relatively unreliable.
A typical solution to the above problem is disclosed in U.S. Pat. No. 4,888,733 issued Dec. 19, 1989 to Kenneth J. Mobley. The memory disclosed in the Mobley patent pulses the ferroelectric capacitor in one direction and stores the developed charge on a first temporary storage capacitor, pulses the ferroelectric capacitor in the opposite direction and stores the developed charge on a second temporary storage capacitor, and then compares the stored charges on the two storage capacitors. Thus, this memory essentially compares two states of the same capacitor taken one after the other in a time interval that is too short for aging or other changes to take place. However, this solution triples the length of time it takes to read a memory, thus this memory is not competitive with state-of-the-art memories which require fast read times. Further, the extra temporary storage capacitors are linear capacitors, which take up significant additional room in the memory, so a memory according to the Mobley design is relatively bulky and is not competitive in a memory market where memory chips are increasingly more dense. There are many other multi-capacitor/multi-transistor ferroelectric memories that have been proposed to solve the above problems, some of which have been incorporated into commercial products. All of them are both significantly less dense than conventional DRAMs and are slower.
Ferroelectric memories also are subject to problems relating to the fact that, unlike DRAMS and other memories based on linear capacitance, a "read voltage" must be placed across the ferroelectric memory to read it. Because in all viable memory architectures cells are in arrays, when the read voltage is placed across the selected cell, some non-selected cells also experience a voltage, called a "disturb voltage". This "disturb voltage" can alter the state of the cell and result in an erroneous data state. In architectures in which the plate line is parallel to the bit line, such as the Koike et al. reference, all the capacitors in the same row as the selected cell are connected across their bit and plate lines when the plate line voltage is applied. Thus, a significant disturb voltage of the same order of magnitude of the read voltage is placed across these nonselected cells. For architectures in which the bit line is perpendicular to the plate line, such as in those of the Toda patent, the nonselected capacitors connected to the selected plate line are not connected to their bit lines when the plate voltage is applied. Thus, the disturb voltage is less, but still significant.
The above problems, particularly the aging problem and the "disturb" problem, are most severe in the fastest and densest memory architectures, such as the Koike et al. architecture. Thus, commercial applications of ferroelectric memories have up to now been limited to relatively slow and bulky architectures, such as the Mobley design. It would be highly desirable to have a ferroelectric memory architecture that was faster and less bulky than the Mobley design, yet was not subject to the problems of fatigue and aging. Such a memory design that also avoided the "disturb" voltage problem, would be a significant advance in the art.
3. Solution to the Problem
The present invention solves the above problem by providing a ferroelectric memory architecture that provides safe, reliable sensing while at the same time being as fast or faster than any prior art design.
The present invention solves the above problems by providing a ferroelectric memory having two capacitors and two switches in each memory cell. The cell architecture is arranged so that, when the cell is read, the linear charge from the two capacitors cancels. Further, the architecture insures that any change in the ferroelectric properties due to aging will also cancel out when the cell is read.
An essential aspect of the invention is that the plate and bit lines are parallel and, for a given memory cell, the bit line is driven and the plate line is read. The parallel plate and bit line architecture results in the nonselected capacitors connected to the selected plate line being disconnected from its corresponding bit line when the bit line is driven. Further, since the plate line is read, the voltage change on the plate line is on the order of tens or a few hundred millivolts, rather than on the order of volts as in the prior art architectures in which the plate line is driven. Thus, any disturb voltage is a factor of ten to a hundred times less than that of prior art designs. Since in ferroelectric memories the effect of a disturb voltage drops off non-linearly and at a faster rate than the voltage, errors due to disturb voltages are more than a hundred times less than in prior art memories.
Since the effect of aging is canceled and the effect of disturb voltages is reduced by a factor of a hundred or more, the memories according to the invention are far safer and more reliable than prior art ferroelectric memories.
In the preferred embodiment, there are two bit lines for each plate line, with one of the capacitors in each cell connected to its corresponding bit line through a switch, and the other capacitor in each cell connected to the other bit line. For both capacitors, the electrode not connected to the bit line through the switch is connected to the cell plate line. Preferably, the switch is a transistor, although it can also be a diode or other switch.
The invention provides a ferroelectric integrated circuit memory comprising: a ferroelectric memory cell; a plate line; and a bit line; the plate line parallel to the bit line; the memory cell connected between the plate line and the bit line; a drive circuit for applying a read voltage across the memory cell; and an output circuit providing an output signal representative of the signal on the plate line after the read voltage is placed across the memory cell. Preferably, the bit line comprises a first bit line and a second bit line, and the memory cell comprises a first ferroelectric capacitor, a first switch, a second ferroelectric capacitor and a second switch, the first switch connected to the first bit line and the first ferroelectric capacitor connected between the first switch and the plate line; the second switch connected to the second bit line and the second ferroelectric capacitor connected between the second switch and the plate line. Preferably, the first switch and the second switch are transistors. Preferably, the output circuit includes an output line and plate line amplifier for applying the voltage on the plate line to the output line. Preferably, the drive circuit includes a bit line driver.
In addition, the invention provides a ferroelectric integrated circuit memory comprising: a first bit line and a second bit line; a plate line; and a memory cell comprising: a first ferroelectric capacitor, a second ferroelectric capacitor, a first switch and a second switch; the first switch connected between the first bit line and one electrode of the first ferroelectric capacitor, the second switch connected between the second bit line and one electrode of the second ferroelectric capacitor, and the other electrodes of the first and second capacitors connected to the plate line. Preferably, the memory also includes a word line, the first switch comprises a first transistor having a gate, the second switch comprises a second transistor having a gate, and the word line is connected to the gates of the first and second transistors. Preferably, the first and second ferroelectric capacitors are essentially identical. Preferably, the memory further comprises a shunt system for equalizing the voltage across the first capacitor and equalizing the voltage across the second capacitor when the memory cell is not selected to be read or written to. Preferably, the shunt system comprises a first shunt transistor connected between the node connecting the first transistor and the first capacitor and the plate line, and a second shunt transistor connected between the node connecting the second transistor and the second capacitor and the plate line, and a shunt line connected to the gates of the shunt transistors. Preferably, the shunt line is parallel to the word line. Preferably, the plate line is parallel to the bit lines.
The invention also provides a method of operating a ferroelectric integrated circuit memory of the type comprising a first bit line and a second bit line, a plate line, and a memory cell comprising: a first ferroelectric memory element and a second ferroelectric memory element; a first switch and a second switch, the first switch connected between the first bit line and the first ferroelectric memory element, the second switch connected between the second bit line and the second ferroelectric memory element, the ferroelectric memory elements connected to the plate line; the method comprising the steps of: writing a logic state into the ferroelectric memory elements by driving the first and second bit lines to the same voltage while the switches are connecting the bit lines and the memory elements; and reading the logic state by driving the first and second bit lines to different voltages and sensing a voltage on the plate line. Preferably, the method further comprises the step of electrically shunting the node between the first switch and the ferroelectric memory element and the node between the second switch and the second ferroelectric memory element to the plate line to equalize the voltage across the first ferroelectric memory element and to equalize the voltage across the second ferroelectric memory element when the memory cell is not being written to or read. Preferably, the step of writing comprises driving the first and second bit lines to either the system supply voltage, Vdd, or zero volts while holding the plate line at 1/2 Vdd. Preferably, the step of reading further comprises placing the plate line at a voltage of 1/2 Vdd prior to the step of reading. Preferably, the memory further includes an output line, and the step of sensing the voltage on the plate line comprises driving the input line to the same voltage as the plate line and sensing the voltage on the output line.
The invention further provides a method of operating a ferroelectric integrated circuit memory of the type comprising a memory cell comprising: a first ferroelectric element, a second ferroelectric element, and a conducting line, the first and second ferroelectric elements electrically connected to or electrically connectable to the conducting line; the method comprising the steps of: writing a logic state into the ferroelectric memory elements by placing a voltage across them; and reading the logic state by: causing the first ferroelectric element to transfer a first linear charge to the conducting line, causing the second ferroelectric element to transfer a second linear charge to the conducting line, and causing one of the ferroelectric elements to transfer a ferroelectric switching charge to the conducting line, wherein the first linear charge is essentially equal to and opposite in sign to the second linear charge so that the first and second linear charges essentially cancel, and thereafter sensing the voltage on the conducting line. Preferably, the step of causing one of the ferroelectric elements to transfer a ferroelectric switching charge to the conducting line comprises: effecting a transfer of a first ferroelectric switching charge to the conducting line when the ferroelectric elements are in a first polarization state, and effecting a transfer of a second ferroelectric switching charge to the conducting line when the ferroelectric elements are in a second polarization state, wherein the first and second ferroelectric switching charges are of opposite signs so that one causes the voltage on the conducting line to drop and the other causes the voltage on the conducting line to rise.
The invention not only provides a ferroelectric memory that is far safer and more reliable than prior art ferroelectric memories, but it is also especially fast because the plate line is not driven. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.